PCIe serves as the bus standard within servers, with data transfer rates continuously improving. In August 2025, the PCI-SIG association announced that the PCIe 8.0 specification under development will increase data rates to 256 GT/s, with an expected release in 2028. The lane configuration of PCIe is a critical factor determining the performance of PCIe devices. The number of lanes sets the upper limit for PCIe slot quantity and length. As PCIe lane counts rise, demand for PCIe slots is anticipated to increase accordingly. Benefiting from ongoing server CPU upgrades, the PCIe generation and lane count compatible with server CPUs are expected to progressively advance, creating additional demand opportunities across the related industry chain.
PCIe is a high-speed serial computer expansion bus standard used for data exchange between the CPU and other devices such as hard drives, network cards, and sound cards. The PCIe bus standard utilizes a serial design, addressing the industry challenge faced by the parallel design of the PCI bus, where bandwidth could not be further increased due to signal integrity issues. The PCIe bus standard undergoes continuous updates, leading to consistent improvements in data transfer rates and performance. In 2019, PCIe 5.0 achieved a transfer rate of 32 GT/s, with single-lane bandwidth increasing to approximately 4 GB/s, enabling a throughput of 128 GB/s in an x16 configuration.
The number of PCIe lanes adaptable within server CPUs is gradually increasing, expanding the demand potential for PCIe slots. The lane configuration is a key determinant of PCIe device performance, commonly denoted by numbers like x1, x4, x8, and x16, which indicate how many independent PCIe lanes are utilized. Physically, PCIe interfaces typically appear as long slots on motherboards, available in four sizes: x1, x4, x8, and x16. Intel's 6th-generation server CPUs can configure up to 88 PCIe 5.0 lanes for efficiency cores, a 10% increase compared to the 5th generation, and up to 96 PCIe lanes for performance cores, representing a 20% increase. The PCIe lane count dictates the maximum number and length of PCIe slots. As the number of PCIe lanes grows, the demand for PCIe slots is likely to rise in tandem.
Server CPUs are evolving towards compatibility with PCIe 6.0, generating incremental demand space for PCIe Retimer chips. Intel's 6th-generation server CPUs already support PCIe 5.0. AMD's next-generation EPYC server processor, codenamed "Venice," is expected to be the first to adopt PCIe 6.0, with a potential launch in 2026. While the PCIe protocol is developing rapidly with increasing transfer rates, the physical size of servers remains largely unchanged due to industrial standards. This constraint leads to higher insertion losses across the entire link as the protocol advances, reaching 36 dB in the PCIe 5.0 era. Furthermore, the PCIe specification includes a precise insertion loss budget; for PCIe 6.0, this budget is 32 dB, meaning designs must ensure the total signal loss during transmission does not exceed this limit. PCIe Retimer chips can extend interface transmission distances and improve signal quality, addressing issues in data centers and servers such as signal timing misalignment, high loss, and poor integrity during high-speed, long-distance data transmission via the PCIe protocol.
Regarding investment targets, it is advisable to monitor: FIT HON TENG (06088) (a PCIe slot supplier), MONTAGE TECH (06809) (a PCIe Retimer chip supplier), and Wantong Development (600246.SH) (which acquired PCIe Switch chip supplier Data Ferry Technology).
Potential risks include slower-than-expected adoption of PCIe technology, weaker-than-anticipated server demand, and delays in the penetration of new-generation server CPUs.