Intel is pursuing a new memory architecture to contest the dominance of high-bandwidth memory (HBM), though its commercial prospects remain distant.

A patent application disclosed by Intel last week reveals its "Cross-Batch Memory" (XBM) architecture. This design aims to bypass the reliance on silicon interposers in current HBM, replacing traditional DRAM and its ultra-wide interfaces with back-end-of-line transistors and serial UCIe interconnects to substantially reduce packaging costs.

Reports indicate the target commercialization timeline for XBM is set for after 2030, aligning with the schedule for Intel's jointly developed ZAM memory architecture with SAIMEMORY, a subsidiary of SoftBank.

The HBM market is currently led by South Korean manufacturers, with dual pressures of tight supply and high costs driving the industry to seek alternatives. Intel's disclosed patent introduces a new variable into this competitive landscape, though analysts note that ecosystem barriers and platform compatibility issues will be major obstacles for XBM's market entry.

XBM Architecture: Replacing Wide Parallel Interfaces with UCIe Serial Links

According to the patent, the core of the XBM architecture involves connecting DRAM modules to UCIe I/O modules operating at 32 GT/s, with I/O signals routed through a base die.

The capacity per die in an XBM stack ranges from 0.5GB to 5GB. Each sub-channel consists of 12 data modules, with an 8-layer XBM stack accommodating up to 96 data modules and a 16-layer stack reaching 192, with a channel operating frequency of 2GHz.

In terms of packaging, XBM supports multiple configurations, including Memory-on-Package (MoP), enabling higher bandwidth and capacity within a smaller form factor. This flexibility is seen as one of XBM's potential advantages over existing HBM solutions.

Back-End DRAM Process: Enhancing Area Efficiency and TSV Density

A key innovation of XBM at the process level is the adoption of a 1T1C (one-transistor-one-capacitor) back-end DRAM structure.

This approach fabricates transistors in the back-end-of-line (BEOL) metal layers rather than the front-end silicon substrate, significantly improving area efficiency. This frees up more space for through-silicon vias (TSVs), enabling higher memory density and bandwidth.

This design directly addresses core challenges of current HBM. Traditional HBM requires microbump processes for vertically stacking DRAM chips, which incurs higher manufacturing costs, while silicon interposers further add wiring complexity and overall cost. The XBM architecture is proposed to overcome these limitations.

The Formidable Lead of SK Hynix and Samsung

Although XBM presents technical appeal, its potential to disrupt the existing competitive order remains in question.

It is noted that SK Hynix and Samsung Electronics have invested years in cost-reduction technologies like standard chiplets, UCIe, and fan-out packaging, building a significant first-mover advantage in cost optimization.

A more critical barrier lies at the ecosystem level. The global AI accelerator ecosystem, centered on NVIDIA, is now highly optimized for the existing HBM architecture and its wide parallel interfaces. Transitioning to an alternative memory architecture faces high costs related to platform compatibility and software adaptation. This means that even if XBM proves technically competitive, its large-scale commercial deployment must overcome substantial industry inertia.

With XBM's commercialization window projected for after 2030, HBM is expected to remain the mainstream solution for AI chip high-bandwidth memory needs for the foreseeable future. Intel's patent primarily represents an exploration of a technological direction rather than an immediate challenge to the current market structure.