Domestic Silicon Wafer Unicorn Updates IPO Prospectus, Aims to Raise 4.965 Billion Yuan

Deep News
Oct 30

Shanghai Super Silicon Semiconductor Co., Ltd. has recently updated its IPO prospectus, planning to raise over 4.9 billion yuan.

01 Fundraising Plan The company intends to raise 4.965 billion yuan, which will be allocated to three projects: "Expansion of 300mm Thin-Layer Silicon Epitaxial Wafers for Integrated Circuits," "R&D of High-End Semiconductor Silicon Materials," and "Working Capital Supplement." Among these, 2.965 billion yuan will be invested in the expansion of 300mm thin-layer silicon epitaxial wafers for integrated circuits.

02 Company Overview Founded in 2008, Shanghai Super Silicon specializes in the R&D, production, and sales of 300mm and 200mm semiconductor silicon wafers. The company also offers contract processing services, including wafer regeneration and silicon rod post-processing.

The company operates a 300mm silicon wafer production line with a designed capacity of 800,000 wafers per month and a 200mm line with a capacity of 400,000 wafers per month. Its products are mass-produced for advanced process chips, including NAND Flash, DRAM (including HBM), Nor Flash, and logic chips.

Its products are sold to major wafer fabs worldwide, including those in mainland China, Taiwan, Europe, the U.S., Japan, and Singapore. The company has established bulk supply partnerships with 18 of the world's top 20 integrated circuit firms, earning significant industry recognition.

03 Financial Performance During the reporting periods, the company's main business revenue was 909.5 million yuan, 923 million yuan, 1.3221 billion yuan, and 753 million yuan, respectively. Net profits attributable to shareholders were -802.9 million yuan, -1.0436 billion yuan, -1.2992 billion yuan, and -736.5 million yuan, with cumulative losses exceeding 3.8 billion yuan.

04 Key Products Semiconductor silicon wafers are critical materials for producing integrated circuits, discrete devices, and sensors. They are categorized by size (6-inch, 8-inch, 12-inch), manufacturing process (polished wafers, epitaxial wafers, annealed wafers, SOI wafers), dopant type (P-type, N-type), doping concentration (light/heavy doping), and application (prime wafers, test wafers, dummy wafers).

The company's main products include 300mm and 200mm silicon wafers, primarily P-type with some phosphorus-doped N-type wafers.

1) 300mm Silicon Wafers - Polished wafers: Used in NOR Flash, NAND Flash, DRAM (including HBM), DDIC, and BCD devices. The company collaborates with a leading global HBM client. - Epitaxial wafers: Thin-layer epitaxial wafers for CMOS logic circuits, Flash memory, and CIS devices. Mass production began in Q4 2022, with multiple global semiconductor firms adopting or certifying the product.

2) 200mm Silicon Wafers - Polished wafers: Low-COP and COP-Free wafers for CMOS logic, BCD, analog circuits, and PMIC. - Epitaxial wafers: For CMOS logic, Flash memory, Power MOSFET, and CIS devices. - Annealed wafers: Used in CMOS logic, Flash memory, and DDIC analog circuits. The company is among the few global suppliers of stable 200mm annealed wafers. - SOI wafers: For MEMS, power devices, pressure sensors, and CMOS logic circuits.

3) Contract Processing - Wafer regeneration: Reprocessing used monitor and dummy wafers to meet new wafer standards. - Silicon rod post-processing: Slicing, grinding, and polishing customer-provided silicon rods into finished wafers.

05 Key Processes 1) Crystal Growth: Uses the Czochralski method to produce single-crystal silicon rods. 2) Post-Processing: Includes cutting, grinding, polishing, cleaning, and inspection. 3) Epitaxial Growth: Forms new silicon epitaxial layers on polished wafers. 4) Annealing: Reduces COP defects and improves wafer flatness. 5) SOI Processing: Uses hydrogen ion implantation and layer splitting for SOI wafers.

06 Workforce As of June 2025, the company and its subsidiaries employ 1,657 full-time staff: - 8.27% administrative, 13.10% R&D, 75.86% production, 2.78% sales. - Education: 1.03% PhD, 5.01% master’s, 35.79% bachelor’s, 58.18% associate degree or below. - Age: 48.40% under 30, 38.56% 31–40, 10.20% 41–50, 2.84% over 51.

07 Milestones - 2008: Founded. - 2011: Became TSMC’s strategic partner; passed 200mm wafer regeneration certification. - 2012: Won TSMC’s "Outstanding Supplier Performance Award." - 2016: Developed 200mm/300mm silicon rods and launched 200mm wafers. - 2018: Shipped first 300mm pilot-line wafers; broke ground on Shanghai BigFab. - 2020: Completed Series A/A+ funding; BigFab operational. - 2022: Secured Series B/B+ funding. - 2023: Recognized as Shanghai’s key innovative enterprise. - 2025: Named Shanghai’s high-tech enterprise and manufacturing champion.

Product Evolution: Since inception, the company has expanded from 200mm to 300mm wafers, epitaxial wafers, and SOI products.

Disclaimer: Information sourced from public filings and company website.

Disclaimer: Investing carries risk. This is not financial advice. The above content should not be regarded as an offer, recommendation, or solicitation on acquiring or disposing of any financial products, any associated discussions, comments, or posts by author or other users should not be considered as such either. It is solely for general information purpose only, which does not consider your own investment objectives, financial situations or needs. TTM assumes no responsibility or warranty for the accuracy and completeness of the information, investors should do their own research and may seek professional advice before investing.

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