JPMorgan has once again raised its shipment forecast for Alphabet's TPU chips, projecting volumes of 3.7 million units in 2026 and 5 million units in 2027, primarily driven by the ongoing expansion of Taiwan Semiconductor Manufacturing's CoWoS packaging capacity and robust market demand.

According to the bank's analyst team led by Gokul Hariharan, the latest research report increases the CoWoS capacity forecast for 2026 and 2027 by 8% and 13% respectively, reflecting TSMC's new capacity construction in the second half of 2026 and throughout 2027. TSMC's CoWoS capacity is expected to reach 115,000 wafers per month by the end of 2026, with external suppliers, primarily ASE and Amkor, providing an additional 12,000 to 15,000 wafers per month. This marks the second time the bank has raised its CoWoS capacity forecast within three months.

JPMorgan indicated that the capacity increase is mainly fueled by rising demand from the ASIC supply chain. TSMC's capacity expansion focus is concentrated on CoWoS-L technology, with some 65nm front-end capacity (Fab 14 and Fab 12) beginning to be used for LSI/interposer manufacturing. Meanwhile, CoWoS-S supply is expected to remain largely stable, and CoWoS-R is increasingly outsourced to packaging and testing houses like ASE.

Strong TPU demand is driving the upward revision of capacity forecasts. Based on strong demand signals from both the back-end and front-end supply chains, JPMorgan has again raised its shipment forecast for Alphabet's TPUs. Analysts now expect TPU shipments to reach 3.7 million units in 2026 and 5 million units in 2027, higher than previous estimates.

To meet TPU demand, JPMorgan has increased its estimated CoWoS wafer allocation for Broadcom to 230,000 wafers in 2026 and 350,000 wafers in 2027. For MediaTek, allocations are projected at 18,000 wafers in 2026 and 55,000 wafers in 2027. The TPU v7 (Ironwood) and v8 series (Broadcom's AX version and MediaTek's X version) are expected to constitute the majority of shipments during 2026-2027.

Currently, all TPU capacity is handled using TSMC's CoWoS-S technology. While certification is underway at Amkor and ASE to address rising demand, progress is relatively slow as TSMC is unlikely to expand its CoWoS-S capacity. Consequently, JPMorgan does not anticipate significant TPU shipments from outsourced assembly and test providers in 2026. The v9 series TPU, based on a 2nm process, is expected to enter small-volume production with Broadcom by the end of 2027; this chip will utilize 3D SoIC packaging and CoWoS-L technology, representing higher technical complexity.

NVIDIA's allocation remains largely flat, while progress on AMD and AWS projects varies. JPMorgan maintains its 2026 CoWoS allocation for NVIDIA at 700,000 wafers, albeit with a slight product mix adjustment. Due to HBM4 readiness issues, mass production of the Rubin series is delayed by 1-2 months, leading to a minor shipment reduction, while GB300 shipments have been increased. Analysts project approximately 400,000 to 500,000 H200 chips will be packaged by Amkor in 2026.

For 2027, JPMorgan has raised NVIDIA's CoWoS allocation by 4%, reflecting stronger demand for Rubin and Rubin Ultra. TSMC will handle all Chip-on-Wafer processes for NVIDIA GPUs, while the substrate portion will be outsourced to ASE. The Vera CPU project will commence with TSMC's CoWoS-R but is expected to transition to Amkor or ASE by late 2026 or early 2027.

AMD's CoWoS forecast remains largely unchanged at 90,000 wafers for 2026 and 120,000 wafers for 2027. However, 2026 shipments are highly concentrated in Q4 (55,000 to 60,000 wafers), primarily because MI450 is scheduled to begin mass production in August-September. Given multiple project challenges—including Serdes issues, SoIC yield, extremely large package size, and rack-level integration—there is a risk of delay into 2027.

AWS's Trainium project forecast has been slightly reduced due to timing issues, with 2026 shipments now expected to be 2.1 million units (1.5 million Trn3 and 600,000 Trn2), although the total lifecycle volume remains unchanged. JPMorgan's supply chain checks indicate that only CoWoS wafers led by Alchip and Annapurna are currently visible, while the project led by Marvell has not yet entered mass production.

The proportion of outsourcing to packaging and testing houses is increasing, and equipment suppliers are set to benefit. Even with rapid growth, TSMC's CoWoS capacity remains severely constrained. The company will prioritize supporting key GPU and AI ASIC projects, leaving smaller or less critical projects to outsourced providers. JPMorgan expects ASE to benefit from the AMD Venice CPU, NVIDIA Vera CPU, and portions of the Trainium3 and TPU projects in late 2026 and 2027, while continuing its role as a core outsourcing partner for TSMC's substrate and wafer probe processes.

Amkor is anticipated to gain incremental business from NVIDIA's H200, Broadcom's networking chips, the Vera CPU, and potentially some TPU orders eventually. JPMorgan forecasts that outsourced providers will contribute approximately 12,000 to 15,000 wafers per month of effective Chip-on-Wafer capacity by the end of 2026. Intel's EMIB-T technology is also being considered for some projects, including small-volume TPU projects for MediaTek and Broadcom in 2027.

JPMorgan believes that strong demand for CoWoS, WMCM, and FOCoS provides clear visibility throughout 2026 for Taiwanese advanced packaging equipment suppliers, including Grand Process Technology, Scientech, and All Ring. Equipment suppliers anticipate CoWoS demand will grow year-over-year, with new capacity additions of approximately 40,000 to 50,000 wafers per month, higher than the roughly 35,000 wafers per month added in 2025. Analysts project that equipment shipments from these suppliers could increase by 20% to 30% or more in 2026.